Vaishnaw says all six Semicon 2.0 pillars are now notified

Union Minister Ashwini Vaishnaw, who holds the Electronics and Information Technology, Railways and Information and Broadcasting portfolios, said on Monday, 31 August 2026, that notifications for all six pillars of Semicon 2.0 have been issued, with the India Semiconductor Mission as the nodal agency. The statement, carried in media-briefing reports the same day, is a policy-completion claim: the architecture is notified, and applicants now face a live scheme rather than a waiting room of draft pillars.

The six pillars, spanning ten categories in the minister’s telling, are design covering intellectual property, chips, systems-on-chip and the Design Linked Incentive route; machines and materials; more fabrication capacity across silicon, compound semiconductors, photonics, sensors, MEMS and display; ATMP and OSAT assembly and test; research and development; and talent. In short, Semicon 2.0 is being sold as a full-stack push rather than a single fab subsidy.

On talent, Vaishnaw claimed India had trained 85,000 semiconductor engineers in four years against what had been framed as a ten-year target, and that a new target seeks one lakh more. Students in Tier-II and Tier-III cities, he said, had designed more than 250 chips. He also projected that India could approach about 10 percent of the global semiconductor market in the coming years, with the ecosystem expected to create 50,000 to 60,000 direct jobs.

Process claims accompanied the vision. Approvals were cited on timelines of 200, 150 and 90 days in different tracks, with one project reaching commercial production thirteen months after groundbreaking. Projects generally run up to six years; the scheme is open for applications for three years; a mid-term review is due after three years. The Ministry of Electronics and Information Technology is to budget fiscal support. The India Semiconductor Mission may use C-DAC on design and deployment work, and deep-tech awards are slated from 2026.

Semiconductor politics in India often outruns semiconductor production. Monday’s briefing matters because it asserts that the notification stage for Semicon 2.0 is complete. Whether fabs, OSAT lines and design wins follow at the claimed speed is an execution test that will show up in factory gates and export bills, not in podium adjectives. This cutting records the minister’s notified-pillars claim, the 85,000 engineers figure, the one-lakh additional talent target, the job-band estimate, and the scheme’s three-year application window — and invents no company-by-company capacity numbers beyond that briefing. India’s semiconductor story will be believed when packaged chips leave Indian lines at predictable yield, not when every pillar is merely notified. Still, notification is a real administrative gate: without it, investors cannot file, and state packages cannot dock to a central scheme. Vaishnaw’s 31 August claim closes that gate. The next public proofs are application volumes, approval letters inside the cited 90-to-200-day bands, and whether the 85,000-engineer talent pipeline shows up in hiring at fabs and design houses.